The need for a high-density block alterable memory devices is ever increasing. Cellular phones, memory sticks, digital cameras, laptop computers, and personal data assistants are a few examples of small devices that demand higher density memories. These devices require alterable memories because their contents change every time they are in use. For example, the size of a memory stick is as small as a pen but it can store 256 MB memory. The memory stick has a Universal Standard Bus (USB) port that can plug into another USB memory port of a computer to transfer the data from the hard drive of that computer. Therefore, the memory stick and other similar devices such as camera memories need a high-density alterable memory device to erase old data and store new data. The Electrically erasable programmable read only memory (EEPROM) common in the industry cannot be used in these applications because EEPROM is not alterable under normal operation conditions.
A typical block alterable memory device employs flash memory to program, read, or erase memory cells. With reference to FIG. 1, a flash memory 100 is a memory array which is arranged in rows 102 and columns 106. Each row 102 has N+1 memory cells connecting to source lines S0-SN. The first memory cell in the row 102 belongs to column BL0 and the Nth memory cell belongs column BLN. Therefore, there are N+1 columns in the flash memory array 100. The gates of all the cells within a column 106 are coupled together to form a wordline WLi 102. There are M+1 wordlines or rows in the flash memory array 100, ranging from WL0 to WLM. The sources of the cells in each column are coupled together and coupled to the select lines 104, ranging from S0 to SN. The drains of the cells in each row are coupled together to form a bitline 106, ranging from BL0 to BLN. The flash array 100 enables users to electrically program and erase information stored in a memory cell 110.
Each memory cell 110 in the flash memory matrix 100 is a floating gate transistor. The structure of a floating gate transistor is similar to a traditional MOS device, except that an extra polysilicon strip is inserted between the gate and the channel. This strip is not connected to anything and called a floating gate. The threshold voltage of a floating gate transistor is programmable. The described flash memory 100 uses the Fowler-Nordheim tunneling effect to program a cell 110. Programming is a process wherein electrons are placed in the floating gate. Programming occurs when applying a high voltage between the gate and source, and gate and drain terminals that a high electric field causes injection of carriers into the floating gate. Electrons acquire sufficient energy to become hot and traverse the first oxide insulator, so they get trapped on the floating gate. Programming is done on a bit basis by applying a correct voltage at the bitline 106 of each cell 110.
The floating gate layer allows the cell 110 to be electrically erased through the gate. Erase and program operations of the memory array 100 can be done on more than one cell at a time. However, the alterable flash memory device has reliability and durability problems because the voltages for erasing and programming are very high.
With reference to Table 1 at the end of this specification, in order to achieve block alterable memory, the memory cell 110 in the flash memory array 100 as shown in FIG. 1 needs to apply +10 volts or −10 volts across the wordline WLi 102, the source line Si 104, and the bitline BLi 106. Accordingly, the placement of such high voltages to a single memory cell transistor 110 presents reliability and durability problems. Over long periods of time, placing high voltages on the memory device 100 may alter a program stored in each cell 110.
One prior art solution to this problem (for example, U.S. Pat. No. 5,066,992 to T. C. Wu) is shown in FIG. 2A. This solution places an extra select transistor 202A in series with a flash memory cell 210A. The gate of the additional select transistor 202A is coupled to the select line S0 to SN, the drain 204A is coupled to the bitline BL0 to BLN 214A, and the source 206A is coupled to the drain of the flash cell. Thus, when a select line Si is ON, each selected transistor connected to the select line Si is turned ON. As a result, the voltage of the drain of the flash cell 210A is proportional to the voltage of the bitline Bi. During a reading cycle, the bitline 214A is open, the select line Si is grounded, and the wordline WLi is at negative program voltage VD. Thus, a program stored in an EEPROM device 200A remains unaltered. Thus, the memory array 100 lasts longer and avoids the reliability and durability of one-transistor memory cells presented above. However, the two-transistor memory cells require larger areas for manufacturing because each memory cell has two transistors.
Referring to FIG. 2B, various cross-sectional views of a memory array 200B are shown. Memory array 200B is formed on a face of a semiconductor substrate 222B. Substrate 222B is doped with a p-type majority carrier. Bitline BL 214B, select line SEL 202B, wordline WL 208B, and the source are n-type and implanted within substrate 222B at the surface. The gate 208B comprises a first poly layer 209B, a second poly layer 211B, and an inter poly layer 212B. Accordingly, column lines 214B and 206B serves as a source and drain of transistors which are used in forming memory cells contained within memory array 200B. Each of the column lines 214B serves as a source of one memory cell or a drain of an adjacent cell. However, this solution dedicates large sections on the semiconductor substrate to the alterable block function. An undesirably low density flash memory results. Consequently, the industry has a need for a memory device structure which has block alterable capability without dedicating semiconductor substrate area to that function.
U.S. Pat. No. 4,783,766 to Samachisa et al. describes a memory cell of a block alterable EEPROM in which a single control gate is common to both the floating gate memory cell and the select transistor device. However, the device is formed using a different process flow from that of flash memory devices, thus requiring a separate masking sequence.
U.S. Pat. No. 6,420,753 to Hoang describes a similar structure to that of the Samachisa patent. It is stated that these memory cells can be manufactured without requiring additional processing steps from those of comparable flash memories.